MIKROPROCESORY PRO VÝKONOVÉ SYSTÉMY. Speciální obvody a jejich programování v C 2. díl. České vysoké učení technické Fakulta elektrotechnická

MIKROPROCESORY PRO VÝKONOVÉ SYSTÉMY Speciální obvody a jejich programování v C 2. díl České vysoké učení technické Fakulta elektrotechnická Ver.1.10 J. Zděnek, 2017

Compare Unit The following three screens illustrate a different configurations of Compare Unit, which is often used, for example, to generate PWM modulation for a three-phase asynchronous motor. The principle of this unit (following picture): The Up-down Counter counts from zero to the continuously adjustable maximum value and then automatically starts the decrement back to zero. It generates the so-called carrier wave (Carrier Wave) The unit contains two digital comparators that compare the state of the bidirectional counter with the contents of the programmable comparator registers. If the event of a match, the unit generates a logical 0 level if the counter counts up or the logical level 1 if the counter is sweeping down (subtracts). The so-called modulation wave (Modulation Wave) The output value is further adjusted (delayed) so that the output that generates the complementary signal for the transistors of one inverter leg is not triggered at the same time (Dead Time) When changing the counting direction of the counter (zero, max), the unit sets an interrupt request and the new content of the corresponding comparator registrs are loaded. A1B14MIS Mikroprocesory pro výkonové systémy 09 2

Compare Unit A1B14MIS Mikroprocesory pro výkonové systémy 09 3

Compare Unit second config The following screen shows the block diagram of a Compare Unit config for one leg. The comparator has three such branches for generating a total of six output pulses for three three-phase full bridge transistors for supplying a three-phase asynchronous motor (Induction Motor) The two-way counter is common to all three branches. Phase shift of pulses of individual branches (for motor power supply) is done by the software by correct filling all six comparator registers (generation of modulation wave. The overall block diagram of the compare unit for generating six PWM outputs with short-circuit protection as the Dead Timer circuit is shown in the second following screen. Output PWM signals from a microcontroller can not directly power up transistors (voltage levels, pulse potential, desired current). Thus, a transformation element called Transistor Driver is inserted between the outputs of the PWM modulator from the microcontroller and the transistors. A1B14MIS Mikroprocesory pro výkonové systémy 09 4

Compare Unit - single chanel A1B14MIS Mikroprocesory pro výkonové systémy 09 5

Compare Unit general view Carrier Wave Code (Kód nosné vlny) Int Žádost o obsluhu Driver (Budič tranzistorů Clock (Takt) Up-Down Counter (Obousměrný čítač) + Compare Unit1 Společná reference Dead Time & Output Logic Compare Unit2 Dead Time & Output Logic + + Induction Machine (Třífázový asynchronní motor) Compare Unit3 Dead Time & Output Logic A1B14MIS Mikroprocesory pro výkonové systémy 09 6

I/O ports The ports of the PIC18F87J11 microcontroller (and the like) can be controlled (read or written) either directly by the software or hardware input or output (eg Capture Unit or Compare Unit,...). The ports are eight-bits wide and are designed to allow any combination of input and output configuration for standard ports, only input (analogue or digital) can be set for the analog input ports. After resetting, all ports (their bits) are set as inputs (in order to avoid electrical conflict with external hardware). The default block diagram of standard port is follows: Each standard port includes: Direction register Output register Input register Control logic for proper write or port bit read A1B14MIS Mikroprocesory pro výkonové systémy 09 7

I/O pin Read of port value LATCH Write to pin register LATCH or PORT Write to direction register LATCH (1=Input, 0=Output) Read of pin state PORT Pin I/O based on TRISx value Input port register A1B14MIS Mikroprocesory pro výkonové systémy 09 8

Port acces controll For a given standard port, the output or input is selected by writing to the appropriate bit register (TRIS): Output - Write in the TRIS bit 0 (mnemo: 0 resembles O) The input to the TRIS bit is written 1 (mnemo: 1 resembles I) If the port is handled by HW (eg Capture / Compare Unit), it is also necessary to enter a programmable value for the I / O in the direction register. After the RESET microcontroller are in TRIS 1 (all Input) By writing to the register (LAT or PORT - the same register) the corresponding values are written to the LATCH registrer. If the relevant TRIS registry bit is set to output (0 - Output), the values from the LATCH register appear on the output pin. The value from the output register is read by reading the LAT. The pin value of the microcontroller is read by reading PORT. Thus, the value of the LATCH output register may be other than the pin of the microcontroller if the bit is not set to output, or the external hardware holds a pin other than LATCH. A1B14MIS Mikroprocesory pro výkonové systémy 09 9

Example: 2x interrupt, 2 interrupt levels The following example demonstrates the use of the PIC18F87J11 microcontroller priority system, which has two levels (higher and lower priority) Interrupt requests generate two timers (TMR0 and TMR1) to set the corresponding request for xif (Interrupt Flag). Interrupt Flag sets the appropriate interrupt source (here any of the timers) in the harware. Interrupt Flag must be reset in ISR by programmer. The xif reset in this example is done at the beginning of the ISR, but the reset can be located anywhere in the ISR. The interrupt level is blocked in the hardware before the next request until the ISR completes. The application processing itself is simulated in this example by incrementing the x and y variables in the corresponding ISRs. The interrupt enable (GIEH, GIEL) must always be placed in the program as the last one after initialization and setting of all other registers and bits used. A1B14MIS Mikroprocesory pro výkonové systémy 09 10

Example: 2x interrupt, 2 interrupt levels A1B14MIS Mikroprocesory pro výkonové systémy 09 11

Example: 1x interrupt, 2 interrupt sources The following example illustrates a situation where multiple interrupt requests are connected to one level (for example, because we want to use 4 interrupt request sources and the PIC18F87J11 microcontroller has only two priority levels. In the example, the TMR0 and TMR1 timers are connected to a higher interrupt priority level, the lower level is not used (its Interrupt Enable Flag IE ie PIE1bits.TMR1IE = 0 (ie FALSE). In ISR at the higher level, xif from each timer is tested and sw flags t0int, t1int are set accordingly. At the same time, it is shown how to transfer the calculation from ISR to background loop. Why to do that? This microcontroller has a small hw stack and it is not appropriate in ISR to build extensive user programs and call functions. The interrupt enable bits (GIEH, GIEL) must always be placed in the program as the last one after initialization and setting of all other registers and bits used. Both GIEH and GIEL flags must be set to 1 (TRUE) even if one of two interrupt priority levels is not used. A1B14MIS Mikroprocesory pro výkonové systémy 09 14

Example: 1x interrupt, 2 interrupt sources A1B14MIS Mikroprocesory pro výkonové systémy 09 15

Example: Capture Unit period measurement The following two screens resemble the Capture Unit block diagram and the timing of its Let's recall the purpose of the Capture Unit. The unit allows to remove the delay from the actual event arrival time (input impulse signal edge), by reading the reference timer in the ISR (the actual edge arrival time is stored in the Capture Register). This eliminates unacceptable errors when measuring high frequency signals (ie a short period). To program the Capture Unit, an input signal is required. In hardware we need to connect it to the input. However, it is preferable to debug the MPLAB Simulator program, where an input signal generator is available A1B14MIS Mikroprocesory pro výkonové systémy 09 19

Example: Capture Unit period measurement A1B14MIS Mikroprocesory pro výkonové systémy 09 20

Example: Capture Unit period measurement To debug the Capture Unit, an input signal is required. In hardware, we need to connect it to the input of the microcontroller. However, the program can be debugged in the MPLAB Simulator, where an input signal generator named Stimulus In the MPLAB menu, we find it in "Debugger-> Stimulus". Stimulus has several modes to generate the input signal to inputs in the Simulator. In the following screen, a Capture Unit program is used to debug the input signal timing from the processor clock. The input of the Capture Unit 1 is pin RC2. The start-up stimulus waits for 1000 steps (it's optional), and then every 500 steps generates the edge, ie the period of the generated signal is 1000 steps (see next screen). This is followed by a Capture Unit program with Timer1 reference timer. For this example, it is not necessary to monitor the timer overflow, its connection to the lower level of the interrupt is only demonstrative. The variable period must have the same dimension (here 16 bits) as the Capture Register to make the modulo 16 run correctly (the preposition for the example above is that the timer overflows only once (not multiple times) when measuring longer periods. A1B14MIS Mikroprocesory pro výkonové systémy 09 22

Example: Capture Unit period measurement Two 8 bit variables into one 16bit A1B14MIS Mikroprocesory pro výkonové systémy 09 27

Example: Capture Unit period measurement The following screen shows in the "Watch" window that the measured period using the Capture Unit and the input from the Stimulus signal generator is exactly the expected 1000 steps of the processor clock, independent of the timer reference timer 1 from which the time information is taken from the Capture Register. The "Watch" window is in the "View-> Watch" menu. A1B14MIS Mikroprocesory pro výkonové systémy 09 28

Example: Compare Unit PWM generation The following two screens resemble a Compare Unit block diagram and time diagram when using it. Recall the purpose of the Compare Unit. The unit allows to eliminate the delay between the required signal edge generating time and the actual edge time if the edge was generated by the software in the ISR. Compare Unit allows you to pre-program the type and time (calculated in the reference timer code) of the future generated edges in advance in the ISR. The desired future edge time is programmed into the Compare Register and the type of future edge (ascending, descending) into the Event Register. In this way, the Compare Unit together with the software generates an output signal (PWM) exactly in relation to the stepping of the reference timer. Let's also recall (and from the following example, it is clear) that the Compare Unit itself does not know anything, the software must be serviced. For debugging with the Compare Unit, we use the simulator in MPLAB and the Viewed Simulator Logic Analyzer. When tuning in hardware, you need to use the best digital oscilloscope to view the generated signal. A1B14MIS Mikroprocesory pro výkonové systémy 09 30

Compare Unit A1B14MIS Mikroprocesory pro výkonové systémy 09 31

Compare Unit principle A1B14MIS Mikroprocesory pro výkonové systémy 09 32

Example: Compare Unit PWM generation The following example (somewhat longer) demonstrates the use of the Compare Unit. Both levels of interrupt are used. Compare Unit in this example generates PWM with fixed period and variable active PWM (log 1). The Timer1 is reference timer for the Compare Unit. The ISR in the higher priority programes the time and type (upward, downward) of next generated edges. The active part of the PWM (i.e., log 1) is swept in a lower priority ISR that responds to the Timer0 overflow. PWM has Dead Time at both ends of the generated period. In this example, note: Program Structures (Few Functions) Appropriate Program Flags (Software Flags) using structure type structure (structure "status"). Symbolic choice of program constants. Initialize timers and Compare Unit. ISR structures in both priority layers. A1B14MIS Mikroprocesory pro výkonové systémy 09 33

Example: Compare Unit PWM generation A1B14MIS Mikroprocesory pro výkonové systémy 09 34

Example: Compare Unit PWM generation The following screen shows the MPLAB (SIM) simulator and the Simulator Logic Analyzer (MPLAB) logic analyzer. The top screen captures the generated fixed period of PWM (10000) timer steps, and the active part of the PWM (Duty Cycle) is just over 50%. The bottom screen then shows the time difference between the PWM edge generated by the Compare Unit (ie, hardware) and the edge-generated software (RD0 output), see ISR for interrupt processing from Compare Unit ie void CCP1_int (void). In actual use, the active part of the PWM (log 1) will be controlled, for example, by a man-operated sensor or better from the controller output. A1B14MIS Mikroprocesory pro výkonové systémy 09 44

MIKROPROCESORY PRO VÝKONOVÉ SYSTÉMY Speciální obvody a jejich programování v C 2. díl KONEC České vysoké učení technické Fakulta elektrotechnická