Evropský sociální fond Praha & EU: Investujeme do vaší budoucnosti Praktika návrhu číslicových obvodů Dr.-Ing. Martin Novotný Katedra číslicového návrhu Fakulta informačních technologií ČVUT v Praze Miloš Bečvář, Martin Novotný, 2006-2011 1
Lecture Outline Entity Architecture Process 2
VHDL language constructs Entity Architecture Process Configuration Package Library 3
Entity, Architecture 4
Comments Everything after -- is a comment Comments end with a new line ------------------------------------------------------------ -- This is a comment ------------------------------------------------------------ entity HALFADD is -- this is also a comment 5
Describes interface only Entity No definition of behavior or internal structure entity MULTIPLEXER is port( A,B,SEL : in bit; Y : out bit ); end MULTIPLEXER; A B SEL SELNON INV AND1 AND2 MULTIPLEXER ASEL OR1 BSEL Y Note: ENTITY, IS, PORT, IN, OUT and END are reserved words of VHDL BIT is a data type VHDL is strictly typed language. 6
Entity entity MULTIPLEXER is port( A,B,SEL : in bit; Y : out bit ); end MULTIPLEXER; bit: values 0 and 1 only MULTIPLEXER A AND1 ASEL SELNON INV OR1 Y B SEL AND2 BSEL library IEEE; use IEEE.std_logic_1164.all; entity MULTIPLEXER is port( A,B,SEL : in std_logic; Y : out std_logic ); end MULTIPLEXER; std_logic: values 0, 1, Z, X, L, H, W, U, - Defined in package std_logic_1164 7
Architecture Describes behavior and/or internal structure of entity Must be associated with a specific entity Single entity can have many architectures Architectural constructs: Processes (sequential programs communicating using signals) Component instantiations (represent structure) Concurrent statements (dataflow description) Architecture is a concurrent environment! 8
Architecture architecture MUX_BODY of MULTIPLEXER is -- declarative part: signal SELNON, ASEL, BSEL : std_logic; Entity name Internal signals -- declarations of: -- internal signals -- components -- constants, data types, A SELNON AND1 MULTIPLEXER ASEL -- executive part: INV OR1 Y B -- processes SEL AND2 BSEL -- component instantiations -- end MUX_BODY; 9
Processes 10
Process Section containing sequential statements Exists inside an architecture Multiple processes interact concurrently connected by signals CLKGENPR : process CLK <= 0 ; wait for 10 ns; CLK <= 1 ; wait for 10 ns; end process CLKGENPR; DFFPR : process (CLK, RESET) if RESET= 1 then Q <= 0 ; elsif CLK EVENT and CLK= 1 then Q <= D; end if; end process DFFPR; Process CLKGENP interacts with process DFFPR using signal CLK. 11
Process VHDL is a concurrent language! => processes run concurrently So-called cooperative multitasking (UNIX: preemptive multitasking) processes must suspend themselves Each process must contain at least one wait statement (note: sensitivity list is a special case of wait statement) Process itself is an infinite loop ABC : process A <= 0 ; wait for 10 ns; B <= 1 ; wait on C, D; Y <= C and D; B <= 0 ; wait until A = 1 ; X <= C; end process ABC; Process is suspended for 10 ns (of simulation time) (in the mean time other processes are run) Process is suspended until an event on signal C or signal D occurs Process is suspended until an event on signal A occurs and condition is satisfied When the end of the process is reached, the process jumps to the ning 12
Processes in the architecture architecture MUX_BODY of MULTIPLEXER is signal SELNON, ASEL, BSEL : std_logic; INV : process A SELNON <= not(sel); wait on SEL; end process; SELNON INV AND1 MULTIPLEXER ASEL OR1 Y AND1 : process ASEL <= A and SELNON; wait on A, SELNON; end process; B SEL AND2 BSEL -- processes AND2, OR1 follow end architecture MUX_BODY; 13
Process with a sensitivity list MUXPR : process if SEL = 0 then Y <= A; else Y <= B; end if; wait on SEL, A, B; end process MUXPR; MUXPR : process (SEL, A, B) if SEL = 0 then Y <= A; else Y <= B; end if; end process MUXPR; Process with sensitivity list must not contain any WAIT statements. Typical usage: synthesizable RTL code. 14
Process with wait statements clkgenpr: process clk<= 0 ; wait for 10 ns; clk<= 1 ; wait for 10 ns; end process clkgenpr; WAIT statements define points where process execution suspends. More powerful Typical usage: testbenches (behavioral description of models in verification environment). Can be used for describing circuit on algorithm level. (commonly called behavioral level). 15